The invention is applicable in electronics, for mounting an integrated circuit in a signal processing device, and more particularly for connecting an integrated circuit to a printed circuit board (PC board) of such an apparatus. Ordinarily, a VISI chip is mounted in a package comprising at least one thermally conductive tagboard supporting the integrated circuit; input/output terminals; and an interconnect structure comprising conductors connecting the input/output terminals of the package to the integrated circuit. Among the input/output terminals of the package, the signal terminals are distinguished from the supply terminals intended for receiving various predetermined external electrical potentials. Similarly, in the interconnect structure, the signal conductors are distinguished from the supply conductors, which serve to route the supply potentials to the integrated circuit.
A package for a VLSI chip must meet very stringent conditions. On the one hand, the reactive component of the supply conductors must be reduced to a minimum. This is ordinarily done by a decoupling device incorporated in the package. The decoupling device ordinarily includes conductor faces, which are connected to the plates of at least one decoupling capacitor and respectively receive the various potentials applied to the supply terminals of the package. Effective decoupling is done at the level of the connection points of the conductor faces with the conductors connected to the capacitor. Taking into account the very low self-induction of the conductor faces, it follows that the decoupling takes place virtually at the level of the connection points of the conductor faces with the supply conductors of the interconnect structure. Hence in order to comprise very short connections, the closer these connection points are to the integrated circuit, the more efficient the decoupling; on the other hand, the decoupling is more efficient, the greater the capacitance of the capacitor, the lower its internal self-induction, and the lower the self-induction of its connections with the conductor faces. Generally, a function of low ohmic resistance distribution of the supply potentials, by the intermediary of the supply conductors. is added to the action of the decoupling device upon the supply conductors. This function is essentially performed by the conductor faces of the decoupling device, which make the package virtually insensitive to variations in the energy required for good functioning of the integrated circuit. On the other hand, the package must be as inexpensive as possible, which in turn requires elements that are simple to construct and assemble. Secondarily, other conditions may be required, such as that the disconnectable.
One known provision intended to meet these conditions is described in European patent application No. 0 166 634. The package is of the "chip carrier" type, including a thermally conductive tagboard supporting the integrated circuit; signal terminals and supply terminals; an interconnect structure in the form of a multilayer ceramic frame supported by the tagboard and surrounding the integrated circuit; and a decoupling device comprising a ceramic cap that covers the frame of the interconnect structure and includes conductor faces connected to at least one decoupling capacitor and to the peripheral connection points of the innerconnect structure. Thus these points are geometrically distant from the integrated circuit over the entire width of the frame, such that the electrical length of the supply conductors remains relatively great, resulting in an increased reactive component (both capacitive and inductive), which is prejudicial to the good functioning of the integrated circuit. The structure of this package also proves to be relatively complex and hence expensive, as well as bulky. It should also be noted that this package is not well suited to refrigeration of the integrated circuit. A good adaptation would necessitate disposing the input/output terminals of the package toward the printed decoupling circuit and would complicate the structure of the package considerably.
This prior art document more generally illustrates the problems encountered with the use of ceramic to make a highperformance package for a very large scale integration circuit. One problem is shrinkage of the co-fired ceramic, which limits the precision with which the conductors can be positioned in a conductive layer of a ceramic interconnect structure. However, ceramic is often a preferred material, because of its good electrical characteristics, its sturdiness and the tight sealing that it provides.